74ACT899QC

Number of Channels per Chip : 8
Output Type : 3-State
Packaging : Tube
Logic Type : CMOS
Supply Voltage - Max : 5.5 V
Maximum Operating Temperature : + 85 C
High Level Output Current : - 24 mA
Low Level Output Current : 24 mA
Supply Voltage - Min : 4.5 V
Output Level : CMOS
Input Level : TTL
Logic Family : ACT
Package / Case : PLCC-28
Propagation Delay Time : 11.5 ns


Features:

Latchable transceiver with output sink of 24 mA
Option to select generate parity and check or "feed-through" data/parity in directions A-to-B or B-to-A
Independent latch enable for A-to-B and B-to-A directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
May be used in system applications in place of the 280
May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity)


Pinout




Specifications

Supply Voltage (V_CC).................. −0.5V to +7.0V
DC Input Diode Current (I_IK)
    V_I = −0.5V ......................................... −20 mA
    V_I = VCC + 0.5V................................. +20 mA
DC Input Voltage (V_I) .........−0.5V to V_CC + 0.5V
DC Output Diode Current (I_OK)
    V_O = −0.5V........................................  −20 mA
    V_O = V_CC + 0.5V +20 mA
DC Output Voltage (V_O) ......−0.5V to V_CC + 0.5V
DC Output Source
    or Sink Current (I_O)............................ ±50 mA
DC V_CC or Ground Current
    per Output Pin (I_CC or I_GND)............... ±50 mA
Storage Temperature (T_STG)... −65°C to +150°C
DC Latch-Up Source or Sink Current .... ±300 mA
Junction Temperature (T_J)..........................140°C


Description

The 74ACT899QC is a 9-bit to 9-bit parity transceiver with transparent latches. The 74ACT899QC can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The ACT899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.