74ACT533

· I_CC and I_OZ reduced by 50%
· Eight latches in a single package
·3-STATE outputs drive bus lines or buffer memory address registers
· Outputs source/sink 24 mA
· Inverted version of the ACT373
· TTL-compatible inputs

Supply Voltage (V_CC)........ - 0.5V to + 7.0V
DC Input Diode Current (I_IK)
V_I = - 0.5V .................- 20 mA
V_I = V_CC + 0.5V ..............+ 20 mA
DC Input Voltage (V_I)..... -0.5V to V_CC + 0.5V
DC Output Diode Current (I_OK)
V_O = - 0.5V................. - 20 mA
V_O = V_CC + 0.5V ..............+ 20 mA
DC Output Voltage (V_O) ....- 0.5V to V_CC + 0.5V
DC Output Source
or Sink Current (I_O) ...... ......± 50 mA
DC V_CC or Ground Current
per Output Pin (I_CC or I_GND) ........± 50 mA
Storage Temperature (T_STG) ..- 65°C to + 150°C
DC Latchup Source
or Sink Current ..............± 300 mA
Junction Temperature (T_J)
PDIP .....................140°C
Supply Voltage (V_CC).......... 4.5V to 5.5V
Input Voltage (V_I)............. 0V to V_CC
Output Voltage (V_O)............ 0V to V_CC
Operating Temperature (T_A).... -40°C to +85°C
Minimum Input Edge Rate DV/Dt
V_IN from 0.8V to 2.0V
V_CC @ 4.5V, 5.5V............ . 125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.

The 74ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data of the 74ACT533 appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.