74ACT280

` HIGHSPEED: t<sub>PD</sub> = 4 ns (TYP.) atV<sub>CC</sub> =5V
` LOWPOWERDISSIPATION:
   I_CC =4 mA (MAX.) at T_A =25 ^oC
` COMPATIBLEWITH TTL OUTPUTS
   V<sub>IH</sub> =2V(MIN),V<sub>IL</sub> = 0.8V(MAX)
` 50W TRANSMISSIONLINEDRIVING CAPABILITY
` SYMMETRICAL OUTPUT IMPEDANCE:
   |I<sub>OH</sub>| = I<sub>OL</sub> = 24mA (MIN)
` BALANCEDPROPAGATIONDELAYS:
   t_PLH t_PHL
` OPERATINGVOLTAGERANGE:
   V<sub>CC</sub> (OPR)= 4.5Vto 5.5V
` PINANDFUNCTION COMPATIBLEWITH 74 SERIES280
` IMPROVEDLATCH-UP IMMUNITY

AbsoluteMaximumRatingsarethose values beyond whichdamage to the device may occur. Functional operation under these condition isnot implied.

The 74ACT280 is an advanced high-speed CMOS 9BIT PARITY GENERATOR - CHECKER fabricated with sub-micron silicon gate and double-layer metal wiring C²MOS technology. It is ideal for low power applications mantaining high speed operation similar to eqivalent Bipolar Schottky TTL.

It is composed of nine data inputs (A to I) and odd/even parity outputs (ODD and EVEN). The nine data inputs control the output conditions.When the number of high level input is odd,ODD output is kept high and EVEN output low.Conservely, when the output is even, EVEN output is kept high and ODD low.

The IC of the 74ACT280 generates either odd or even parity making it flexible application.

The word-length capability of the 74ACT280 is easily expanded bycascading.

The 74ACT280 is designed to interface directly HighSpeed CMOS systems with TTL, NMOS and CMOS output voltage levels.

All inputs and outputs of the 74ACT280 are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.