Features: ·ICC reduced by 50%·Edge-triggered D-type inputs·Buffered positive edge-triggered clock·Asynchronous common reset·True and complement output·Outputs source/sink 24 mA·ACT175 has TTL-compatible inputsPinoutSpecificationsSupply Voltage (VCC) .........−0.5V to +7.0VDC Input Diode Curr...
74ACT175: Features: ·ICC reduced by 50%·Edge-triggered D-type inputs·Buffered positive edge-triggered clock·Asynchronous common reset·True and complement output·Outputs source/sink 24 mA·ACT175 has TTL-compat...
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Supply Voltage (VCC) .........−0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V ...................−20 mA
VI = VCC + 0.5V............. ... +20 mA
DC Input Voltage (VI) .......−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V ....................−20 mA
VO = VCC + 0.5V ........... ......+20 mA
DC Output Voltage (VO) .......−0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO) ................±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND) .......... .±50 mA
Storage Temperature (TSTG) ........−65 to +150
Junction Temperature (TJ)............... 140
PDIP.......................... 140
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications
The 74ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.