74ACT11174

The 74ACT11174 is designed as hex D-type flip-flop with clear which contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse.

The eight features of the 74ACT11174. (1)Applications include: buffer/ storage registers, shift registers, pattern generators. (2)Flow-through architecture optimizes PCB layout. (3)Center-pin Vcc and GND pin configurations minimize high-speed switching noise. (4)EPIC (enhanced-performance implanted CMOS) 1um process. (5)500mA typical latch-up immunity at 125°C. (6)Package options include plastic small-outline packages and standard plastic 300mil DIPs. (7)Inputs are TTL-voltage compatible. (8)Fully-buffered outputs for maximum isolation from external disturbances. Those are all the main features.

Some absolute maximum ratings of the 74ACT11174 have been concluded into several points as follow. (1)Its supply voltage range would be from -0.5V to 7V. (2)Its input voltage range would be from -0.5V to Vcc+0.5V. (3)Its output voltage range would be from -0.5V to Vcc+0.5V. (4)Its input clamp current would be +/-20mA. (5)Its output clamp current would be +/-50mA. (6)Its continuous output current would be +/-50mA. (7)Its continuous current through Vcc or GND would be +/-150mA. (8)Its storage temperature range would be from -65°C to 150°C. It should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to device.

And some electrical characteristics of the 74ACT11174 are concluded as follow. (1)Its Voh would be min 4.4V. (2)Its Vol would be max 0.1V. (3)Its Ii would be max +/-0.1uA. (4)Its Icc would be max 8uA. (5)Its Ci would be typ 4pF. (6)Its clock frequency would be min 0MHz and max 110MHz. (7)Its pulse duration would be min 4ns for CLR low and would be min 4.5ns for CLK high or low. (8)Its setup time before CLK would be min 4ns for data and would be min 1ns for CLR inactive. (9)Its hold time after CLK would be min 0.5ns. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!