PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to V...
74ACT11160: PinoutSpecificationsSupply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V Input voltage range, VI (see...
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This synchronous, presettable 4-bit decade counter features of the 74ACT11160 an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked neously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock-input waveform.
This counter of the 74ACT11160 is fully programmable; that is, it may be preset to any number between 0 and 9. As presetting is ronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock rising edge regardless of the levels of the enable inputs. The clear function for the 74ACT11160 is asynchronous, and a low level at the clear (CLR) input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs.
The carry look-ahead circuitry of the 74ACT11160 provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output. Both count-enable inputs must be held high to count, and ENT is fed forward to enable RCO. RCO thus enabled will produce a high-level pulse while the count is 9 (HLLH). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input.
This counter features of the 74ACT11160 a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.
The 74ACT11160 is characterized for operation from 40°C to 85°C.