Polarity
: Non-Inverting
Input Type
: Single-Ended
Output Type
: Single-Ended
Maximum Operating Temperature
: + 85 C
High Level Output Current
: - 24 mA
Low Level Output Current
: 24 mA
Mounting Style
: Through Hole
Package / Case
: PDIP-20
Packaging
: Tube
Number of Circuits
: 8
Logic Type
: D-Type Flip-Flop
Supply Voltage - Max
: 6 V
Logic Family
: 74AC
Propagation Delay Time
: 13 ns
Features: ICC reduced by 50%
Ideal for addressable register applications
Clock enable for address and data synchronization applications
Eight edge-triggered D-type flip-flops
Buffered common clock
Outputs source/sink 24 mA
See 273 for master reset version
See 373 for transparent latch version
See 374 for 3-STATE version
ACT377 has TTL-compatible inputsPinout
SpecificationsSupply Voltage (VCC).................. −0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V ......................................... −20 mA
VI = VCC + 0.5V................................. +20 mA
DC Input Voltage (VI) .........−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V........................................ −20 mA
VO = VCC + 0.5V +20 mA
DC Output Voltage (VO) ......−0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)............................ ±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)............... ±50 mA
Storage Temperature (TSTG)... −65°C to +150°C
Junction Temperature (TJ)
PDIP ......................................................140°C DescriptionThe 74AC377PC has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register of the 74AC377PC is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
74AC377PC Data Sheet
