74AC280

` HIGHSPEED: t<sub>PD</sub> = 4 ns (TYP.) atV<sub>CC</sub> =5V
` LOWPOWERDISSIPATION:
    I_CC =4 mA (MAX.) at T_A =25 oC
` HIGHNOISEIMMUNITY:
    V<sub>NIH</sub>=V<sub>NIL</sub> =28%V<sub>CC</sub> (MIN.)
` 50 TRANSMISSIONLINEDRIVING CAPABILITY
` SYMMETRICAL OUTPUT IMPEDANCE:
    |I<sub>OH</sub>| = I<sub>OL</sub> = 24mA (MIN)
` BALANCEDPROPAGATIONDELAYS:
    t_PLH t_PHL
` OPERATINGVOLTAGERANGE:
   V<sub>CC</sub> (OPR)= 2V to 6V
` PINANDFUNCTION COMPATIBLEWITH 74 SERIES280
` IMPROVEDLATCH-UP IMMUNITY

AbsoluteMaximumRatingsarethose values beyond whichdamage to the device may occur. Functional operation under these condition isnot implied.

The 74AC280 is an advanced high-speed CMOS 9 BIT PARITY GENERATOR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL.

It is composed of nine data inputs (A to I) and odd/even parity outputs (SODD and SEVEN). The nine data inputs control the output conditions. When the number of high level input is odd,SODD output is kept high and SEVEN output low. Conservely, when the output is even, SEVEN output is kept high and SODD low.

The IC of the 74AC280 generates either odd or even paritymaking it flexible application.

The word-length capability is easily expanded bycascading.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.