74AC11652

Features: ` Independent Registers and Enables for A and B Buses` Multiplexed Real-Time and Stored Data` Inverting Data Paths` Flow-Through Architecture Optimizes PCB Layout` Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise` EPICE (Enhanced-Performance Implanted CMOS) 1-mm ...

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74AC11652 Picture
SeekIC No. : 004248874 Detail

74AC11652: Features: ` Independent Registers and Enables for A and B Buses` Multiplexed Real-Time and Stored Data` Inverting Data Paths` Flow-Through Architecture Optimizes PCB Layout` Center-Pin VCC and GND C...

floor Price/Ceiling Price

Part Number:
74AC11652
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

` Independent Registers and Enables for A and B Buses
` Multiplexed Real-Time and Stored Data
` Inverting Data Paths
` Flow-Through Architecture Optimizes PCB Layout
` Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
` EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process
` 500-mA Typical Latch-Up Immunity at 125



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI< 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±200 mA
Maximum power dissipation at TA = 55 (in still air) (see Note 2) . . . . . . . . . . . . . .1.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150



Description

The 74AC11652 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.

A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11652. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.

Thus, when all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state. The 74AC11652 is characterized for operation from 40°C to 85°C.




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