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74AC11286

Features: • Generates Either Odd or Even Parity for Nine Data Lines• Cascadable for n-Bits Parity• Direct Bus Connection for Parity Generation or for Checking by Using the Parity I/O Port• Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configur...

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SeekIC No. : 004248858 Detail

74AC11286: Features: • Generates Either Odd or Even Parity for Nine Data Lines• Cascadable for n-Bits Parity• Direct Bus Connection for Parity Generation or for Checking by Using the Parity I...

74AC11286 Data Sheet

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Part Number:
74AC11286
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Generates Either Odd or Even Parity for Nine Data Lines
• Cascadable for n-Bits Parity
• Direct Bus Connection for Parity Generation or for Checking by Using the Parity I/O Port
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 to 150
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.


Description

The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

The XMIT control input of the 74AC11286 is implemented specifically to accommodate cascading. When the XMIT is low, the parity tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels. When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port will remain in the high-impedance state during power up or power down to prevent bus glitches.

The 74AC11286 is characterized for operation from 40°C to 85°C.




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