74AC11273

Features: • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators• Flow-Through Architecture to Optimize PCB Layout• Multiple Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise• EPICTM (Enhanced-Performance Implanted CMO...

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74AC11273 Picture
SeekIC No. : 004248857 Detail

74AC11273: Features: • Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators• Flow-Through Architecture to Optimize PCB Layout• Multiple Center-Pin VCC and GND Con...

floor Price/Ceiling Price

Part Number:
74AC11273
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/3/10

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Product Details

Description



Features:

• Applications Include:
     Buffer/Storage Registers
     Shift Registers
     Pattern Generators
• Flow-Through Architecture to Optimize PCB Layout
• Multiple Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
• EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  .0.5 V to 7 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . ±50 mA
Continuous output current, IO (VO = 0 to VCC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . . . . . .±200 mA
Storage temperature range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .65°C to 150°C



Description

These positive-edge-triggered flip-flops implement D-type flip-flop logic with a direct clear input.

Data of the 74AC11273 at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

The 74AC11273 is characterized for operation from 40°C to 85°C.




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