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74AC11239

Features: • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems• Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception• Flow-Through Architecture to Optimize PCB Layout• Center-Pin VCC and GND Configurations to Minimize Hi...

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SeekIC No. : 004248852 Detail

74AC11239: Features: • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems• Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception• Flow-Thr...

74AC11239 Data Sheet

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Part Number:
74AC11239
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
• Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
• Flow-Through Architecture to Optimize PCB Layout
• Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small Outline Packages, and Standard Plastic 300-mil DIPs


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . .    ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . .± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . .  ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . .  . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . 65 to 150


Description

The 74AC11239 circuit is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The 74AC11239 is comprised of two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The 74AC11239 is characterized for operation from 40°C to 85°C.




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