74AC11139

Features:

` Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems
` Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception
` Center-Pin V<sub>CC</sub> and GND Configurations Minimize High-Speed Switching Noise
` EPIC™ (Enhanced-Performance Implanted CMOS) 1-mm Process
` 500-mA Typical Latch-Up Immunity at 125
` Package Options Include Plastic
  Small-Outline (D) and Thin Shrink
  Small-Outline (PW) Packages, and
  Standard Plastic 300-mil DIPs (N)


Pinout




Specifications

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 0.5 V to V_CC + 0.5 V
Output voltage range, V_O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V_CC + 0.5 V
Input clamp current, I^_IK (V_I < 0 or V_I > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . ±50 mA
Continuous output current, I_O (V_O = 0 to V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . ±50 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ±200 mA
Maximum power dissipation at T_A = 55 (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W
                                                                                                        N package . . . . . . . . . . . . . . . . . . . . 1.1 W
                                                                                                        PW package . . . . . . . . . . . . . . . .  . . 0.5 W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150 and a board trace length of 750 mils,except for the N package, which has a trace length of zero.


Description

The 74AC11139 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The 74AC11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The 74AC11139 is characterized for operation from 40 to 85.