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74ABTH16899

Features: •Symmetrical (A and B bus functions are identical)•Selectable generate parity or feed-through parity for A-to-B and B-to-A directions•Independent transparent latches for A-to-B and B-to-A directions•Selectable ODD/EVEN parity•Continuously checks parity o...

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SeekIC No. : 004248812 Detail

74ABTH16899: Features: •Symmetrical (A and B bus functions are identical)•Selectable generate parity or feed-through parity for A-to-B and B-to-A directions•Independent transparent latches fo...

74ABTH16899 Data Sheet

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Part Number:
74ABTH16899
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/18

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Product Details

Description



Features:

•Symmetrical (A and B bus functions are identical)
•Selectable generate parity or "feed-through" parity for A-to-B and B-to-A directions
•Independent transparent latches for A-to-B and B-to-A directions
•Selectable ODD/EVEN  parity
•Continuously checks parity of both A bus and B bus latches as ERRA  and ERRB
•Open-collector ERR output
•Ability to simultaneously generate and check parity
•Can simultaneously read/latch A and B bus data
•Output capability: +64 mA/32mA
•Latch-up protection exceeds 500mA per Jedec Std 17
•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
•Power up 3-State
•Power-up reset
•Live insertion/extraction permitted
•Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs


Pinout

Connection Diagram Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +7.0 V
IIK DC input diode current VI < 0
18 mA
VI DC input voltage3   1.2 to +7.0 V
IOK DC output diode current VO < 0 50 mA
VOUT DC output voltage3 output in Off or High state 0.5 to +5.5 V
IOUT DC output current output in Low state 128 mA
Output in High state -64  mA
Tstg Storage temperature range   65 to 150 °C



Description

   The 74ABTH16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

   Parity error checking of the A and B bus latches is continuously provided with ERRA  and ERRB , even with both buses in 3-State.

   The 74ABTH16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN  parity, and separate error signal output pins for checking parity.




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