74ABTH16841A

Features: • High speed parallel latches• Live insertion/extraction permitted• Extra data width for wide address/data paths or buses carrying parity• Power-up 3-State• 74ABTH16841A incorporates bus-hold data inputs which eliminate the need for external pull-up resistor...

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SeekIC No. : 004248811 Detail

74ABTH16841A: Features: • High speed parallel latches• Live insertion/extraction permitted• Extra data width for wide address/data paths or buses carrying parity• Power-up 3-State• 7...

floor Price/Ceiling Price

Part Number:
74ABTH16841A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• High speed parallel latches
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or buses carrying parity
• Power-up 3-State
• 74ABTH16841A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Output capability: +64mA/32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model



Pinout

  Connection Diagram


Specifications

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.



Description

The 74ABTH16841A  Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity.
The 74ABTH16841A consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state.
Two options are available, 74ABT16841A which does not have the bus-hold feature and 74ABTH16841A which incorporates the bus-hold feature.


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