74ABTH16821A

Features: • 20-bit positive-edge triggered register•Multiple VCC and GND pins minimize switching noise• Live insertion/extraction permitted• Power-up reset• Power-up 3-State• 74ABTH16821A incorporates bus-hold data inputs which eliminate the need for external pu...

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SeekIC No. : 004248807 Detail

74ABTH16821A: Features: • 20-bit positive-edge triggered register•Multiple VCC and GND pins minimize switching noise• Live insertion/extraction permitted• Power-up reset• Power-up 3-...

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Part Number:
74ABTH16821A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 20-bit positive-edge triggered register
•Multiple VCC and GND pins minimize switching noise
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• 74ABTH16821A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs
• Output capability: +64mA/-32mA
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model



Pinout

  Connection Diagram


Specifications

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.



Description

The 74ABTH16821A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and  high output drive.
The 74ABTH16821A has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.
The 3-State output buffers of the 74ABTH16821A are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
Two options are available, 74ABT16821A which does not have the bus-hold feature and 74ABTH16821A which incorporates the bus-hold feature.


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