74ABTH16652

Features: • Independent registers for A and B buses• Multiple VCC and GND pins minimize switching noise• Power-up 3-State• 74ABTH16652 incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs• Power-up reset•...

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SeekIC No. : 004248806 Detail

74ABTH16652: Features: • Independent registers for A and B buses• Multiple VCC and GND pins minimize switching noise• Power-up 3-State• 74ABTH16652 incorporates bus-hold data inputs which...

floor Price/Ceiling Price

Part Number:
74ABTH16652
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/28

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Product Details

Description



Features:

• Independent registers for A and B buses
• Multiple VCC and GND pins minimize switching noise
• Power-up 3-State
• 74ABTH16652 incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs
• Power-up reset
• Live insertion/extraction permitted
• Multiplexed real-time and stored data
• Output capability: +64mA/32mA
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model



Pinout

  Connection Diagram  Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +7.0 V
IIK DC input diode current VI < 0
18 mA
VI DC input voltage3   1.2 to +7.0 V
IOK DC output diode current VO < 0 50 mA
VOUT DC output voltage3 output in Off or High state 0.5 to +5.5 V
IOUT DC output current output in Low state 128 mA
Output in High state -64  mA
Tstg Storage temperature range   65 to 150 °C



Description

   The 74ABTH16652 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

   The 74ABTH16652 transceiver/register consists of two sets of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes HIGH. Output Enable (nOEAB, (nNEBA ) and Select (nSAB , nSBA ) pins are provided for bus management.

   Two options are available, 74ABT16652 which does not have the bus-hold feature and 74ABTH16652 which incorporates the bus-hold feature.


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