74ABTH16373B

Features: *16-bit transparent latch*Multiple VCC and GND pins minimize switching noise*Power-up 3-State*Live insertion/extraction permitted*Power-up reset*3-State output buffers*74ABTH16373B incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to holdunused inp...

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SeekIC No. : 004248799 Detail

74ABTH16373B: Features: *16-bit transparent latch*Multiple VCC and GND pins minimize switching noise*Power-up 3-State*Live insertion/extraction permitted*Power-up reset*3-State output buffers*74ABTH16373B incorpo...

floor Price/Ceiling Price

Part Number:
74ABTH16373B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/18

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Product Details

Description



Features:

*16-bit transparent latch
*Multiple VCC and GND pins minimize switching noise
*Power-up 3-State
*Live insertion/extraction permitted
*Power-up reset
*3-State output buffers
*74ABTH16373B incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold 
  unused inputs
*Output capability: +64mA/32mA
*ICCL 19 mA maximum
*Latch-up protection exceeds 500mA per JEDEC Std 17
*ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
 


Pinout

  Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC
DC supply voltage   0.5 to +7.0 V
IIK
DC input diode current VI < 0
18 mA
VI

DC input voltage3
  1.2 to +7.0 V
IOK
DC output diode current V O< 0
50 mA
VOUT
DC output voltage3
output in Off or High state 0.5 to +5.5 V
IOUT
DC outpputut current output in Low state 128 mA
output in High state 64
Tstg
Storage temperature range   65 to 150 °C



Description

The 74ABTH16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and  high output drive.

The 74ABTH16373B device is a dual octal transparent latch coupled to two sets of eight 3-State output  buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates.

The data on each set of D inputs are transferred to  the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-State output buffers of the 74ABTH16373B are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation.


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