74ABT899CSC

Bus Transceivers 9-Bit Latchable Tran

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74ABT899CSC Picture
SeekIC No. : 00417894 Detail

74ABT899CSC: Bus Transceivers 9-Bit Latchable Tran

floor Price/Ceiling Price

Part Number:
74ABT899CSC
Mfg:
Fairchild Semiconductor
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Quick Details

Logic Type : BiCMOS Logic Family : 74ABT
Number of Channels per Chip : 8 Input Level : TTL
Output Level : TTL Output Type : 3-State
High Level Output Current : - 32 mA Low Level Output Current : 64 mA
Propagation Delay Time : 4.8 ns Supply Voltage - Max : 5.5 V
Supply Voltage - Min : 4.5 V Maximum Operating Temperature : + 85 C
Package / Case : SOIC-28 Packaging : Tube    

Description

Number of Channels per Chip : 8
Output Type : 3-State
Packaging : Tube
Supply Voltage - Max : 5.5 V
Maximum Operating Temperature : + 85 C
Supply Voltage - Min : 4.5 V
Input Level : TTL
Output Level : TTL
High Level Output Current : - 32 mA
Low Level Output Current : 64 mA
Logic Type : BiCMOS
Propagation Delay Time : 4.8 ns
Logic Family : 74ABT
Package / Case : SOIC-28


Features:

Latchable transceiver with output sink of 64 mA
Option to select generate parity and check or "feed-through" data/parity in directions A-to-B or B-to-A
Independent latch enables for A-to-B and B-to-A directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
May be used in systems applications in place of the 543 and 280
May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity)
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF loads
Guaranteed simultaneous switching noise level and dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire power up and power down cycle
Nondestructive hot insertion capability
Disable time less than enable time to avoid bus contention



Pinout

  Connection Diagram


Specifications

Storage Temperature.......................... −65°C to +150°C
Ambient Temperature under Bias........ −55°C to +125°C
Junction Temperature under Bias
    Plastic..................................... ........−55°C to +150°C
VCC Pin Potential to
    Ground Pin.......................................... −0.5V to +7.0V
Input Voltage (Note 2)............................ −0.5V to +7.0V
Input Current (Note 2)...................... −30 mA to +5.0 mA
Voltage Applied to Any Output
    in the Disabled or
    Power-Off State ....................................−0.5V to 5.5V
    in the HIGH State ...................................−0.5V to VCC
Current Applied to Output
    in LOW State (Max)............... twice the rated IOL (mA)
DC Latchup Source Current............................... −500 mA
Over Voltage Latchup (I/O) .......................................10V



Description

The 74ABT899CSC is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction.

The 74ABT899CSC features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.




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