Features: • High speed parallel registers with positive edge-triggered D-type flip-flops
• Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors
• Output capability: +64mA/32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
• Power-up 3-State
• Power-up ResetPinout
Specifications
| SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
| VCC |
DC supply voltage |
|
0.5 to +7.0 |
V |
| IIK |
DC input diode current |
VI < 0 |
18 |
mA |
| VI |
DC input voltage3 |
|
1.2 to +7.0 |
V |
| IOK |
DC output diode current |
VO < 0 |
50 |
mA |
| VOUT |
DC output voltage3 |
output in Off or High state |
0.5 to +5.5 |
V |
| IOUT |
DC output current |
output in Low state |
128 |
mA |
| Tstg |
Storage temperature range |
|
65 to 150 |
°C |
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DescriptionThe 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74ABT821 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.
The 74ABT821 is a buffered 10-bit wide version of the 74ABT374/74ABT534 functions.
The 74ABT821 is a 10-bit, edge triggered register coupled to ten 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates.
The register of the 74ABT821 is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (OE) controls of the 74ABT821 all ten 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
74ABT821 Data Sheet
