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74ABT377A

Features: •Ideal for addressable register applications•8-bit positive edge-triggered register•Enable for address and data synchronization applications•Output capability: +64mA/-32mA•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17•ESD protection exceeds...

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SeekIC No. : 004248737 Detail

74ABT377A: Features: •Ideal for addressable register applications•8-bit positive edge-triggered register•Enable for address and data synchronization applications•Output capability: +64m...

74ABT377A Data Sheet

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Part Number:
74ABT377A
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/8/13

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Product Details

Description



Features:

•Ideal for addressable register applications
•8-bit positive edge-triggered register
•Enable for address and data synchronization applications
•Output capability: +64mA/-32mA
•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
•Power-up reset


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +7.0 V
IIK DC input diode current VI < 0 18 mA
VI DC input voltage3   1.2 to +7.0 V
IOK DC output diode current VO< 0 50 mA
VOUT DC output voltage3 output in Off or High state 0.5 to +5.5 V
IOUT DC output current output in Low state 128 mA
Tstg Storage temperature range   65 to 150 °C



Description

The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E</a>) input is Low.

The register of the 74ABT377A is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

The E</a> input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.




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