Features: · Clock enable for address and data synchronization applications· Eight edge-triggered D-type flip-flops· Buffered common clock· See ABT273 for master reset version· See ABT373 for transparent latch version· See ABT374 for 3-STATE version· Output sink capability of 64 mA, source capabili...
74ABT377: Features: · Clock enable for address and data synchronization applications· Eight edge-triggered D-type flip-flops· Buffered common clock· See ABT273 for master reset version· See ABT373 for transpa...
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The 74ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW.
The register of the 74ABT377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.