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74ABT377

Features: · Clock enable for address and data synchronization applications· Eight edge-triggered D-type flip-flops· Buffered common clock· See ABT273 for master reset version· See ABT373 for transparent latch version· See ABT374 for 3-STATE version· Output sink capability of 64 mA, source capabili...

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SeekIC No. : 004248736 Detail

74ABT377: Features: · Clock enable for address and data synchronization applications· Eight edge-triggered D-type flip-flops· Buffered common clock· See ABT273 for master reset version· See ABT373 for transpa...

74ABT377 Data Sheet

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Part Number:
74ABT377
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Clock enable for address and data synchronization applications
· Eight edge-triggered D-type flip-flops
· Buffered common clock
· See ABT273 for master reset version
· See ABT373 for transparent latch version
· See ABT374 for 3-STATE version
· Output sink capability of 64 mA, source capability of 32 mA
· Guaranteed latchup protection
· High impedance glitch free bus loading during entire power up and power down cycle
· Non-destructive hot insertion capability
· Disable time less than enable time to avoid bus contention


Pinout

Connection Diagram


Specifications

Storage Temperature . . . . . . . . . . . . −65°C to +150°C
Ambient Temperature under Bias . . . −55°C to +125°C
Junction Temperature under Bias . . . −55°C to +150°C
VCC Pin Potential to Ground Pin . . .  . .  .  −0.5V to +7.0V
Input Voltage (Note 2) . . . . . . . . . . . . . .  −0.5V to +7.0V
Input Current (Note 2) . . . . . . . . . . .  −30 mA to +5.0 mA
Voltage Applied to Any Output
    in the Disabled or
    Power-OFF State . . . . . . . . . . . . . .  . . −0.5V to +4.75V
     in the HIGH State . . . . . . . . . . . . . . .  . . . −0.5V to VCC
Current Applied to Output
    in LOW State (Max) . . . . . . . .  Twice the rated IOL (mA)
DC Latchup Source Current . . . . . .    . . . . . . . .  . −500 mA
    (Across Comm Operating Range)
Over Voltage Latchup . . . . . . . . . .  . .   . . .     . VCC + 4.5V


Description

The 74ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW.

The register of the 74ABT377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.




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