74ABT273A

•Eight edge-triggered D-type flip-flops
•Buffered common clock
•Buffered asynchronous Master Reset
•Power-up reset
•See 74ABT377 for clock enable version
•See 74ABT373 for transparent latch version
•See 74ABT374 for 3-State version
•ESD protection exceeds 2000 V per Mil Std 833 Method 3015 and 200 V per machine model.

The 74ABT273A has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register of the 74ABT2952 is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs will be forced Low independent of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP andMR are common elements.