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74ABT273

Features: · Eight edge-triggered D-type flip-flops· Buffered common clock· Buffered, asynchronous Master Reset· See ABT377 for clock enable version· See ABT373 for transparent latch version· See ABT374 for 3-STATE version· Output sink capability of 64 mA, source capability of 32 mA· Guaranteed lat...

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SeekIC No. : 004248723 Detail

74ABT273: Features: · Eight edge-triggered D-type flip-flops· Buffered common clock· Buffered, asynchronous Master Reset· See ABT377 for clock enable version· See ABT373 for transparent latch version· See ABT...

74ABT273 Data Sheet

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Part Number:
74ABT273
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Eight edge-triggered D-type flip-flops
· Buffered common clock
· Buffered, asynchronous Master Reset
· See ABT377 for clock enable version
· See ABT373 for transparent latch version
· See ABT374 for 3-STATE version
· Output sink capability of 64 mA, source capability of 32 mA
· Guaranteed latchup protection
· High impedance glitch free bus loading during entire power up and power down cycle
· Non-destructive hot insertion capability
· Disable time less than enable time to avoid bus contention


Pinout

Connection Diagram


Specifications

Storage Temperature  . . . .  . . . .  . . . . −65°C to +150°C
Ambient Temperature under Bias  . . . . −55°C to +125°C
Junction Temperature under Bias  . . . . −55°C to +150°C
VCC Pin Potential to Ground Pin . . . . . . .  . .−0.5V to +7.0V
Input Voltage (Note 2). . . . . . . . . . .  . . .  .  −0.5V to +7.0V
Input Current (Note 2). . . . . . . .  . . .  . −30 mA to +5.0 mA
Voltage Applied to Any Output
    in the Disabled or
    Power-Off State. . . . . . . . .. .   . . . .  . . .−0.5V to +4.75V
    in the HIGH State . . . . . . . . .. .  . . . .  . .  . −0.5V to VCC
Current Applied to Outpu
    in LOW State (Max) . . . . . .  . . . twice the rated IOL (mA)
DC Latchup Source Current. . . . .   . . . .  . . . .   .   −500 mA
    (Across Comm Operating Range)
Over Voltage Latchup . . . . . .  .  . . . .  . . . .  .   .VCC + 4.5V


Description

The 74ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register of the 74ABT273 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs will be forced LOW independently of Clock or Data of the 74ABT273 inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is required and the Clock and Master Reset are common to
all storage elements.




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