74ABT16646

Features:

 Independent registers for A and B buses
 Multiplexed real-time and stored data
 A and B output sink capability of 64 mA, source capability of 32 mA
 Guaranteed latchup protection
 High impedance glitch free bus loading during entire power up and power down cycle
 Nondestructive hot insertion capability


Pinout




Specifications

Storage Temperature                                               −65°C to +150°C
Ambient Temperature under Bias                             −55°C to +125°C
Junction Temperature under Bias                             −55°C to +150°C
V_CC Pin Potential to Ground Pin                                    −0.5V to +7.0V
Input Voltage (Note 3)                                                  −0.5V to +7.0V
Input Current (Note 3)                                            −30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disable or
Power-Off State                                                             −0.5V to +5.5V
in the HIGH State                                                              −0.5V to V_CC
Current Applied to Output
in LOW State (Max)                                          twice the rated I_OL (mA)
DC Latchup Source Current                                                      −500 mA
Over Voltage Latchup (I/O)                                                              10V



Description

   The 74ABT16646 consists of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls of the 74ABT16646 can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register.