72T54252L6-7BBI

Specifications

Package PBGA 324 Speed 6.7 NS Temperature I Voltage 2.5 V Density 2 Mb Organization 64K x 10 x 4 Access Time 3.8 ns I/O Type 1.5 V HSTL,1.8 V HSTL,2.5 V LVTTL,3.3 V LVTTL Function JTAG,DDR/SDR Family Name TeraSyncDDR Flags Empty/Full,Partial Full,Programmable,Partial Empty Bus Width x10/x20 Architecture Dual/Quad FIFO Timing Type DDR Synchronous


Description

2.5V QUAD TERASYNC
Board Space Savings. Configurable to 2 or 4 FIFOs in a single package. Double Data Rate Port Selectable, Bus Matching, 3.3/2.5/1.8/1.5-V port selectable I/O, Read Echo Outputs 72T54252L6-7BBI