Features: • For convenience, features have been organized to reflect:• Standard features of the 68HC908EY16• Features of the CPU08 Standard features of the MC68HC908EY16 include:• High-performance M68HC08 architecture optimized for C-compilers• Fully upward-compatible...
68HC908EY16: Features: • For convenience, features have been organized to reflect:• Standard features of the 68HC908EY16• Features of the CPU08 Standard features of the MC68HC908EY16 include:...
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• For convenience, features have been organized to reflect:
• Standard features of the 68HC908EY16
• Features of the CPU08 Standard features of the MC68HC908EY16 include:
• High-performance M68HC08 architecture optimized for C-compilers
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• 8-MHz internal bus frequency at 5V
• Internal oscillator requiring no external components:
Software selectable bus frequencies
25 percent accuracy with trim capability to 2 percent
Clock monitor
Option to allow use of external clock source or external
•crystal/ceramic resonator
• 15,872 bytes of on-chip FLASH memory with in-circuit programming
• FLASH program memory security1
• 512 bytes of on-chip random-access memory (RAM)
• Low voltage inhibit (LVI) module
• Internal clock generator module (ICG)
• Two 16-bit, 2-channel timer (TIMA and TIMB) interface modules with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel
• 8-channel, 10-bit successive approximation analog-to-digital converter (ADC)
• Enhanced serial communications interface module (ESCI) for local interconnect network (LIN) connectivity
• Serial peripheral interface (SPI)
• Timebase Module (TBM)
• 5-bit keyboard interrupt (KBI) with wakeup feature
• 24 general-purpose input/output (I/O) pins
• External asynchronous interrupt pin with internal pullup (IRQ)
• System protection features:
Optional computer operating properly (COP) reset
Illegal opcode detection with reset
Illegal address detection with reset
• 32-pin quad flat pack (QFP) package
• Low-power design; fully static with stop and wait modes
• Internal pullups onIRQ and RST to reduce customer system cost
• Standard low-power modes of operation:
Wait mode
Stop mode
• Master reset pin (RST) and power-on reset (POR)
• BREAK module (BRK) to allow single breakpoint setting during in-circuit debugging
• Higher current source capability on nine port lines for LED drive (PTA6/SS, PTA5/SPSCK, PTA4/KDB4, PTA3/KBD3, PTA2/KBD2, PTA1/KBD1, PTA0/KBD0, PTC1/MOSI, and PTC0/MISO)
Characteristic(1) | Symbol | Value | Value |
Supply voltage | VDD | 0.3 to +6.0 | V |
Input voltage | VIn | VSS 0.3 to VDD +0.3 | V |
Maximum current per pin excluding VDD, VSS, and PTA0PTA6 and PTC0-PTC1 |
I | ±15 | mA |
Maximum current for pins PTA0PTA6 and PTC0-PTC1 |
IPTA0IPTA6, IPTC0IPTC1 |
±25 | mA |
Maximum current out of VSS | IMVSS | 100 | mA |
Maximum current into VDD | IMVDD | 100 | mA |
Storage temperature | TSTG | 55 to +150 | °C |