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68HC05H12

Features: •Full-duplex, 3-wire synchronous transfers•Master or slave operation•2.50 MHz (maximum) master bit frequency•5.0 MHz (maximum) slave bit frequency•Four programmable master bit rates•Programmable clock polarity and phase•End-of-transmission interr...

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SeekIC No. : 004238390 Detail

68HC05H12: Features: •Full-duplex, 3-wire synchronous transfers•Master or slave operation•2.50 MHz (maximum) master bit frequency•5.0 MHz (maximum) slave bit frequency•Four progra...

68HC05H12 Data Sheet

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Part Number:
68HC05H12
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

•Full-duplex, 3-wire synchronous transfers
•Master or slave operation
•2.50 MHz (maximum) master bit frequency
•5.0 MHz (maximum) slave bit frequency
•Four programmable master bit rates
•Programmable clock polarity and phase
•End-of-transmission interrupt flag
•Write collision flag protection
•Master-master mode fault protection
•Easy interface to simple expansion parts (PLLs, D/As, latches,
 display drivers, etc.)
•Very low clock rates by reuse of the SCI prescalers.


Pinout

Connection Diagram


Specifications

Rating Symbol Value Unit
Supply Voltage VDD 0.3 to +7.0 V
Supply Voltage for Power Drivers PVDD12 0.3 to +10.0 V
Input Voltage
Normal Operation
Monitor Mode (IRQ Pin Only)		 VIN
VIN		 VSS0.3 to VDD+0.3
VSS 0.3 to 2 *VDD +0.3		 V
V
Current Drain Per Pin IOmax 300 mA
Short Circuit Time for Power Drivers (PE70, PF30) (note 1) tSC 20 ms
Operating Temperature Range TA 40 to +85 °C
Storage Temperature Range TSTG 65 to +150 °C
Write/Erase Cycles EEPROM10   10,000 cycles
Data Retention EEPROM   10 year



Description

The 68HC05H12 specifications:

•HC05 core
•52 PLCC package
•12032 bytes of user (EP)ROM + 240 bytes of monitor ROM + 16
bytes user vectors
•256 bytes of RAM
•256 bytes of EEPROM
•Multipurpose core timer, real time interrupt (RTI), COP watchdog timer
•Two 16-bit timers with two input captures and two output compares each
•Serial peripheral interface (SPI)
•Serial communications interface (SCI)
•4 channel A/D converter (8-bit resolution)
•Keyboard interrupt for 8 I/O lines
•8 channel 8-bit PWM system for control of H-bridge drivers
•12 special power drivers to drive two major gauges and four minor
  gauges, with short circuit detection and slew rate limitation for reduced RFI (EMC)
•Power saving WAIT mode
•2 selectable bus frequencies (slow mode)
•Low voltage reset (LVR) circuitry to hold the CPU in reset




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