670M-03I

Specifications

Temperature I Voltage 3.3 V Package SOIC 16 Speed NA


Description

LOW PHASE NOISE, ZERO DE
The 670M-03I is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of IDT's ClockBlocks family, the part's zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs giving the appearance of no delay through the 670M-03I. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin.

The 670M-03I is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing off chip feedback paths, the 670M-03I can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications.

Packaged in 16-pin SOIC

Available in Pb (lead) free package

Clock inputs from 5 to 160 MHz (see page 2)

Patented PLL with low phase noise

Output clocks up to 160 MHz at 3.3 V

15 selectable on-chip multipliers

Power down mode available

Low phase noise: -111 dBc/Hz at 10 kHz

Output enable function tri-states outputs

Low jitter 15 ps one sigma

Advanced, low power, sub-micron CMOS process

Operating voltage of 3.3 V or 5 V

Industrial temperature range available (-40 to +85°C)