6541

Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
V_IN ..........................................................-0.5V to VCC+1.0V
Storage Temperature (plastic) ....................-65^oC to +150^o
Ambient Temperature .................................-55^oC to +125^o
Junction Temperature ............................................... +125^o
Power Dissipation ........................................................1.0W
Short Circuit Output Current .......................................50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The 6541 is organized as a 131,072 x 24 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using triple-layer polysilicon, double-layer metal technology.

The 6541 offers multiple power and ground pins for improved performance and noise immunity. For increased system flexibility and eliminating bus contention problems, this device offers multiple chip enables (CE#, CE1# and CE2), and output enable (OE#) with this organization. For GVT73128S24 device in 100-pin TQFP package, separate byte enables (BE0#, BE1#, and BE2#) are also available to control individual bytes.

Writing to the 6541 is accomplished by bringing Chip Enables (CE# and CE1#) and Write Enable (WE#) inputs LOW and CE2 HIGH. Reading from the device is accomplished by bringing Chip Enables (CE# and CE1#)LOW and bringing CE2 and Write Enable (WE#) inputs HIGH, along with Output Enable (OE#) being asserted LOW.

The 6541 offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.