Features: • Fast access times: 10, 12, 15and 20ns• Fast OE# access times: 5, 6, 7 and 8ns• Single +3.3V +0.3V power supply• Fully static -- no clock or timing strobes necessary• All inputs and outputs are TTL-compatible• Three state outputs• Center power a...
6540: Features: • Fast access times: 10, 12, 15and 20ns• Fast OE# access times: 5, 6, 7 and 8ns• Single +3.3V +0.3V power supply• Fully static -- no clock or timing strobes necessa...
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The 6540 is organized as a 131,072 x 16 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using triple-layer polysilicon, double-layer metal technology.
This 6540 offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#), separate byte enable controls (BLE# and BHE#) and output enable (OE#) with this organization.
The 6540 offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.