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6539

Test Probes EXTENSION CORD J-

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SeekIC No. : 002788293 Detail

6539: Test Probes EXTENSION CORD J-

6539 Data Sheet

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Part Number:
6539
Mfg:
Pomona Electronics
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description

Tip Style :
Equipment Type :


Features:

• Low standby current: 5ua (max.)
• Low operating current: 1.5mA/MHz (typ.)
• Wide power supply voltage range:
3.0V to 3.6V for GVT73024UL8XX family
2.7V to 3.3V for GVT73024UL8XXB family
2.3V to 2.7V for GVT73024UL8XXC family
1.8V to 2.2V for GVT73024UL8XXD family
• Low data retention voltage: 1.5V (Min)
• Full CMOS 6-transistor memory cell
• Fully static -- no clock or timing strobes necessary
• All inputs and outputs are TTL-compatible
• Three state outputs
• Easy memory expansion with CE1#, CE2 and OE# options
• Automactic power-down when deselected


Pinout

Connection Diagram


Specifications

Voltage on VCC Supply Relative to VSS........-0.3V to +4.0V
VIN ........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) .................-65oC to +150oC
Power Dissipation .......................................................0.7W
Soldering Temperature (10s) ....................................260oC
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

The 6539 is organized as a 131,072 x 8 SRAM using a six-transistor full CMOS memory cell along with lowpower CMOS process, using double-layer polysilicon,double-layer metal technology.

Static design of 6539 eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers two chip enables (CE1# and CE2) along with output enable (OE#) for this organization.

The chip 6539 is enabled when CE1# is LOW and CE2 is HIGH. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.




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