6537

Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V
VIN ........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) .............. ...-55^oC to +125^o
Junction Temperature ..............................................+125^o
Power Dissipation .....................................................1.2W
Short Circuit Output Current ....................................50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The 6537 is organized as a 524,288 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology.

The 6537 offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#) and output enable (OE#) with this organization.

Writing to 6537 is accomplished when write enable (WE#) and chip enable (CE#) inputs are both LOW. Reading is accomplished when (CE#) and (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.