6536

Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V
VIN ........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..................-55^oC to +125^o
Junction Temperature ..............................................+125^o
Power Dissipation .....................................................1.2W
Short Circuit Output Current ....................................50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The 6536 is organized as a 32,768 x 8 SRAM using a four-transistor memory cell with a high performance,silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology.

Static design of 6536 eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers one chip enable (CE#) along with output enable (OE#) for this organization.

The chip 6536 is enabled when CE# is LOW. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected.This allows system designers to meet low standby power requirements.