Features: • Fast access times: 8, 8.5, 10, and 11ns
• Fast clock speed: 100, 90, and 67 MHz
• Provide high performance 2-1-1-1 access rate
• Fast OE# access times: 3.5, 4.0, 4.5, and 5.0ns
• 3.3V -5% and +10% power supply
• Separate isolated output buffer supply compatible with3.3V and 2.5V I/O (VCCQ): 2.375V to 3.6V
• 5V tolerant inputs except I/O's
• Clamp diodes to VSS/VSSQ at all inputs and outputs
• Common data inputs and data outputs
• BYTE WRITE ENABLE and GLOBAL WRITE control
• Three chip enables for depth expansion and addresspipeline
• Address, data and control registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down for portable applications
• High density, high speed packagesPinout
SpecificationsVoltage on VCC Supply Relative to VSS..... -0.5V to +4.6V
VIN ........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ...................-55oC to +125o
Junction Temperature ...............................................+125o
Power Dissipation .......................................................1.6W
Short Circuit Output Current (per I/O).........................20mA
*Stresses greater than those listed under "Absolute MaximumRatings" may cause permanent damage to the device.This is a stressrating only and functional operation of the device at these or anyother conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximumrating conditions for extended periods may affect reliability.
DescriptionThe Galvantech Synchronous Burst SRAM family of 6525 employs high-speed, low power CMOS designs usingadvanced triple-layer polysilicon, double-layer metaltechnology. Each memory cell consists of four transistors andtwo high valued resistors.
The 6525 SRAM integrates 65,536x36 SRAMcells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronousinputs are gated by registers controlled by a positive-edgetriggeredclock input (CLK). The synchronous inputs includeall addresses, all data inputs, address-pipelining chip enable(CE#), depth-expansion chip enables (CE2# and CE2), burstcontrol inputs (ADSC#, ADSP#, and ADV#), write enables(BW1#, BW2#, BW3#, BW4#,and BWE#), and global write(GW#).
Asynchronous inputs of 6525 include the output enable (OE#),burst mode control (MODE), and sleep mode control (ZZ).The data outputs (Q), enabled by OE#, are also asynchronous.Addresses and chip enables are registered with eitheraddress status processor (ADSP#) or address status controller(ADSC#) input pins. Subsequent burst addresses can beinternally generated as controlled by the burst advance pin(ADV#).
Address, data inputs, and write controls of 6525 are registered onchipto initiate self-timed WRITE cycle. WRITE cycles canbe one to four bytes wide as controlled by the write controlinputs. Individual byte write allows individual byte to bewritten. BW1# controls DQ1-DQ8 and DQP1. BW2# controlsDQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24 andDQP3. BW4# controls DQ25-DQ32 and DQP4. BW1#,BW2# BW3#, and BW4# can be active only with BWE#being LOW. GW# being LOW causes all bytes to be written.The 6525 operates from a +3.3V power supply.
All inputs and outputs of 6525 are TTL-compatible. The device isideally suited for 486, PentiumTM, 680x0, and PowerPCTMsystems and for systems that are benefited from a widesynchronous data bus.
6525 Data Sheet
