6264C

The 6264C is designed as a 65536-bit static random access memory organized as 8192 words of 8 bits, fabricated using motorola's second generation high performance silicon gate CMOS technology. Static design of 6264C eliminates the need for external clocks of timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.

6264C has many features. The first one is single 5.0V ± 10% power supply. The second one is output enable feature for increased system flexibility and to eliminate bus contention problems. The third one is 8K x 8 organization. The fourth one is fully static no clock or timing strobes necessary. The fifth one is it would have fast access time which would be 15, 20, 25, 35, 45, 55, 70 ns. The sixth one is it would have low power dissipation which would be 825mW. The seventh one is fully TTL compatible. The eighth one is three state data outputs. That are all the main features.

Some absolute maximum ratings of 6264C have been concluded into several points as follow. The first one is about its power supply voltage which would be from -0.5V to +7.0V. The second one is about its voltage relative to Vss for any pin except Vcc which would be from -0.5V to Vcc+0.5V. The third one is about its output current (per I/O) which would be ±20mA. The fourth one is about its power dissipation which would be 1.0W. The fifth one is about its temperature under bias which would be from -55°C to +125°C. The sixth one is about its storage temperature range which would be from -65°C to +150°C. The seventh one is about its operating temperature range which would be from -55 to +125°C. It should be noted that permanent device damage may occur if absolute maximum ratings of 6264C are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to higher than recommended voltages for extended periods of time could affect device. And so on. For more information please contact us.