613MLF

Specifications

Input Frequency 25 MHz No. of Inputs 1 Temperature C Output Frequency 125 MHz,140 MHz,150 MHz,143.75 MHz,156.25 MHz,157.5 MHz,146.875 MHz Input Type Clock,Crystal No. of Outputs 2 Output Type CMOS Voltage 3.3 V Package SOIC 16 Speed NA Core Supply Voltage (VDD) 3.3 V Output Supply Voltage (VDDO) 2.5 V to. 3.3 V Peak-to-Peak Period Jitter ± 60 ps Pk-to-Pk Output Style SE Input Style Crystal Temp. Grade C


Description

LOW PHASE NOISE CLOCK MUL
The 613MLF is a low cost, low phase noise, high-performance clock synthesizer for any applications that require low phase noise and low jitter. 613MLF is IDT's lowest phase noise multiplier. Using IDT's patented analog and digital Phase-Locked Loop (PLL) techniques, the 613MLF can accept a 25 MHz crystal or clock input, and produces output clocks up to 157.5 MHz.

The 613MLF has separate power supplies for the clock outputs, allowing each output to be run at different voltages. It also allows the core of the chip to operate at 3.3 V, while the output clocks run at either 2.5 V or 3.3 V.

613MLF features:

Packaged in 16-pin SOIC

Available in Pb (lead) free package

Uses a fundamental 25 MHz crystal or clock

Operating voltage of 3.3 V

Separate output voltage supplies which can run at 2.5 V or 3.3 V

Output clocks up to 157.5 MHz

Low phase noise: -110 dBc/Hz at 10 kHz

Low jitter of 36 ps (one sigma)

Advanced, low power, sub-micron CMOS process