5V80001PGGI

Specifications

Temperature I Voltage 3.3 V Package TSSOP 20 Speed NA Output Style Core Supply Voltage (VDD) No. of Outputs Min. Output Frequency Min. Input Frequency Output Supply Voltage (VDDO) No. of Inputs Input Style Max. Output Frequency Max. Input Frequency Temp. Grade Input Data Standard


Description

MOST CLOCK INTERFACE
The 5V80001PGGI is a high performance clock interface for use in MOST? (Media Oriented Systems Transport) enabled systems. 5V80001PGGI can be used in two modes: generating a master clock for the ring, or performing clock/data recovery in a slave node.

5V80001PGGI features:

Packaged in 20-pin TSSOP

-40 to +105°C temperature range

Compliant to AEC Q100

Operating voltage of 3.3 V

5 volt tolerant input for FOT

Low jitter generation

Power-down tri-state mode

Advanced, low-power CMOS process