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5962R9676601QYC

Features: • Devices QML Qualified in Accordance with MIL-PRF-38535• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil' QM Plan• Radiation Hardened EPI-CMOS- Parametrics Guaranteed 1 x 105 RAD(Si)- Transient Upset > 1 x 108 RAD(Si)/s- ...

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SeekIC No. : 004234364 Detail

5962R9676601QYC: Features: • Devices QML Qualified in Accordance with MIL-PRF-38535• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil' QM Plan• Radiation...

5962R9676601QYC Data Sheet

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Part Number:
5962R9676601QYC
Supply Ability:
5000

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Product Details

Description



Features:

• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil' QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 105 RAD(Si)
- Transient Upset > 1 x 108 RAD(Si)/s
- Latch-Up Free > 1 x 1012 RAD(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current 200mA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55oC to +125oC


Pinout

Connection Diagram


Description

The HS-81C55/56RH are radiation hardened RAM and I/O  chips fabricated using the Intersil radiation hardened Self- Aligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation of HS-81C55/56RH is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices.

The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These HS-81C55/56RH are designed for operation utilizing a single 5V power supply




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