5962-9951401QYA

• XQ1701L/XQR1701L
• QML Certified
• Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices
• Simple interface to the FPGA; requires only one user I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
• Supports XQ4000XL/Virtex fast configuration mode (15.0 MHz)
• Available in 44-pin ceramic LCC (M grade) package
• Available in 20-pin SOIC package (XQ1701L only)
• Programming support by leading programmer manufacturers.
• Design support using the Xilinx Allianc™ and Foundation™ series software packages.
• XQR1701L (only)
• Fabricated on Epitaxial Silicon to improve latch performance (parts are immune to Single Event Latch-up)
• Single Event Bit Upset immune
• Total Dose tolerance in excess of 50 krad(Si)
• All lots subjected to TID Lot Qualification in accordance with method 1019 (dose rate ~9.0 rad(Si)/sec)
• XQ1701L (only)
• Also available under the following Standard Microcircuit Drawing (SMD): 5962-9951401. For more information contact hte Defense Supply Center Columbus (DSCC):

The QPro™ series XQR1701L are Xilinx 3.3V high-density configuration PROMs. The XQR1701L are radiation hardened. These devices are manufactured on Xilinx QML certified manufacturing lines utilizing epitaxial substrates and TID lot qualification (per method 1019).

When the FPGA XQR1701L is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access  time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA XQR1701L generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA XQR1701L must both be clocked by an incoming signal. Figure 1 shows a simplied block diagram.

Multiple XQR1701L can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. XQR1701L are compatible and can be cascaded with other members of the family.

For XQR1701L  programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers