574MLFT

Specifications

No. of Inputs 1 Temperature C Input Type CMOS No. of Outputs 4 Output Type CMOS Voltage 3.3 V Package SOIC 8 Speed NA Max. Input Frequency 160 MHz Output to Output Skew 150 ps Device to Device Skew 700 ps Jitter 250 ps C-to-C Core Supply Voltage (VDD) 3.3 V to 5 V Output Supply Voltage (VDDO) 3.3 V to 5 V


Description

ZERO DELAY, LOW SKEW BUF
The 574MLFT is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the 574MLFT provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements of 574MLFT connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.

574MLFT features:

Packaged in 8-pin narrow SOIC

Available in Pb (lead) free package

Zero input-to-output delay

Four 1X outputs

Output to output skew is less than 150 ps

Output clocks up to 160 MHz at 3.3 V

External feedback path for output edge placement

Spread Smart? technology works with spread spectrum clock generators

Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V

Advanced, low power, sub-micron CMOS process

Operating voltage from 3.0 to 5.5 V

Industrial temperature version available