571MLFT

Specifications

No. of Inputs 1 Temperature C Input Type CMOS No. of Outputs 2 Output Type CMOS Voltage 3.3 V Package SOIC 8 Speed NA Max. Output Frequency 160 MHz Output to Output Skew 850 ps Multiplier/Divider /2,x2 Jitter ± 80 ps Pk-to-Pk Core Supply Voltage (VDD) 3.3 V to 5 V Output Supply Voltage (VDDO) 3.3 V to 5 V


Description

LOW PHASE NOISE ZERO DELA
The 571MLFT is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. ICS introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570. The 571MLFT, part of IDT's ClockBlocks? family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay 571MLFT feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other.

571MLFT features:

Packaged in 8-pin SOIC

Available in Pb (lead) free package

Can function as low phase noise x2 multiplier

Low skew outputs. One is ÷ 2 of other

Input clock frequency up to 150 MHz at 3.3 V

Phase noise of better than - 100 dBc/Hz from 1 kHz to 1 MHz offset from carrier

Can recover poor input clock duty cycle

Output clock duty cycle of 45/55 at 3.3 V

High drive strength for >100 MHz outputs

Full CMOS clock swings with 25mA drive capability at TLL levels

Advanced, low power CMOS process

Operating voltages of 3.0 to 5.5 V