570AILF

Specifications

Temperature I Voltage 3.3 V Package SOIC 8 Speed NA


Description

MULTIPLIER AND ZERO DELAY
The 570AILF is a high-performance Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. The 570AILF is part of IDT's ClockBlocks? family, and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The 570AILF incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high impedance state.

The 570AILF is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.

570AILF features:

Packaged in 8-pin SOIC

Available in Pb (lead) free package

Pin-for-pin replacement and upgrade to ICS570M

Functional equivalent to AV9170 (not a pin-for-pin replacement).

Low input to output skew of 300 ps max (>60 MHz outputs)

Low skew (100ps) outputs. One is ÷ 2 of other

Ability to choose between 14 different multipliers from 0.5X to 32X

Output clock frequency up to 168 MHz at 3.3 V

Can recover degraded input clock duty cycle

Output clock duty cycle of 45/55

Power-down and Tri-State mode

Passes spread spectrum clock modulation

Full CMOS clock swings with 25 mA drive capability at TLL levels

Advanced, low power CMOS process

ICS570B has an operating voltage of 3.3 V

ICS570A has an operating voltage of 5.0V

Industrial temperature version available