54LS109

This 54LS109 contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering of 54LS109 occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is high or low as long as setup and hold times are not violated. A low logic level of 54LS109 on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.