Features: ` ICC reduced to 40.0 A` Ideal buffer for MOS microprocessor or memory` Eight edge-triggered D flip-flops` Buffered common clock` Buffered asynchronous master reset` TTL input and output level compatible` TTL levels accept CMOS levels` IOL = 48 mA (Com) 32 mA (Mil)` NSC 5474FCT273 is pin...
54FCT273PCQR: Features: ` ICC reduced to 40.0 A` Ideal buffer for MOS microprocessor or memory` Eight edge-triggered D flip-flops` Buffered common clock` Buffered asynchronous master reset` TTL input and output l...
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` ICC reduced to 40.0 A
` Ideal buffer for MOS microprocessor or memory
` Eight edge-triggered D flip-flops
` Buffered common clock
` Buffered asynchronous master reset
` TTL input and output level compatible
` TTL levels accept CMOS levels
` IOL = 48 mA (Com) 32 mA (Mil)
` NSC 5474FCT273 is pin and functionally equivalent to IDT 5474FCT273
` Military product compliant to MIL-STD-883 and Standard Military Drawing5962-87656
If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications
Terminal Voltage with Respect to GND
(VTERM)
54FCT -0.5 to +70V
74FCT -0.5 to +70V
Temperature Under Bias (TBIAS)
74FCT -55 to +125
54FCT -65 to +135
Storage Temperature (TSTG)
74FCT -55 to +125
54FCT -65 to +150
DCOutputCurrent(IOUT ) 120mA
Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and outputinput loading variables National does not recom-TM mend operation of FACT FCT circuits outside databook specifications
The 54FCT273PCQR has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously
The register 54FCT273PCQR is fully edge-triggered The state of each D in-put one setup time before the LOW-to-HIGH clock tran-sition is transferred to the corresponding flip-flop's Q out-put All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The 54FCT273PCQR is useful for applications where the true output only is required and the Clock and Master Reset of 54FCT273PCQR are common to all storage elements