54FCT273

Features: Eight edge-triggered D flip-flopsBuffered common clockBuffered, asynchronous Master ResetSee 'FCT377 for clock enable versionSee 'FCT373 for transparent latch versionSee 'FCT374 for TRI-STATE(R) versionOutput sink capability of 32 mA, source capability of12 mATTL input and output level c...

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54FCT273 Picture
SeekIC No. : 004233355 Detail

54FCT273: Features: Eight edge-triggered D flip-flopsBuffered common clockBuffered, asynchronous Master ResetSee 'FCT377 for clock enable versionSee 'FCT373 for transparent latch versionSee 'FCT374 for TRI-ST...

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Part Number:
54FCT273
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/3/10

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Product Details

Description



Features:

Eight edge-triggered D flip-flops
Buffered common clock
Buffered, asynchronous Master Reset
See 'FCT377 for clock enable version
See 'FCT373 for transparent latch version
See 'FCT374 for TRI-STATE(R) version
Output sink capability of 32 mA, source capability of12 mA
TTL input and output level compatible
CMOS power consumption
Standard Microcircuit Drawing (SMD) 5962-8765601



Pinout

  Connection Diagram  Connection Diagram  Connection Diagram


Specifications

Storage Temperature ...................................................-65 to +150
Ambient Temperature under Bias................................. -55
to +125
Junction Temperature under Bias
    Ceramic ....................................................................-55
to +175
VCC Pin Potential to
    Ground Pin .................................................................-0.5V to +7.0V
Input Voltage (Note 2) ...................................................-0.5V to +7.0V
Input Current (Note 2) .............................................-30 mA to +5.0 mA
Voltage Applied to Any Output
    in the Disabled or
    Power-Off State .......................................................-0.5V to +4.75V
    in the HIGH State .........................................................-0.5V to V CC
Current Applied to Output
    in LOW State (Max) ....................................Twice the rated IOL (mA)
DC Latchup Source Current...................................................... -500 mA
    (Across Comm Operating Range)
Over Voltage Latchup ..........................................................VCC + 4.5V



Description

The 54FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register 54FCT273 is fully edge-triggered. The state of each D in- put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop's Q output. All outputs of 54FCT273 will be forced LOW independently of Clock or
DatainputsbyaLOWvoltagelevelontheMRinput.Thede- viceisusefulforapplicationswherethetrueoutputonlyisre- quired and the Clock and Master Reset of 54FCT273 are common to all storage elements.


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