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54F74

Features: *Guaranteed 4000V minimum ESD protectionPinoutSpecificationsStorage Temperature........................... −65°C to +150°CAmbient Temperature under Bias......... −55°C to +125°CJunction Temperature under Bias......... −55°C to +150°CVCC Pin Potential to Ground Pin ........

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SeekIC No. : 004233318 Detail

54F74: Features: *Guaranteed 4000V minimum ESD protectionPinoutSpecificationsStorage Temperature........................... −65°C to +150°CAmbient Temperature under Bias......... −55°C to +125°...

54F74 Data Sheet

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Part Number:
54F74
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/9/16

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Product Details

Description



Features:

*Guaranteed 4000V minimum ESD protection




Pinout

Connection Diagram




Specifications

Storage Temperature........................... −65°C to +150°C
Ambient Temperature under Bias......... −55°C to +125°C
Junction Temperature under Bias......... −55°C to +150°C
VCC Pin Potential to Ground Pin ..................−0.5V to +7.0V
Input Voltage (Note 2)................................ −0.5V to +7.0V
Input Current (Note 2).......................... −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output ...........................................−0.5V to VCC
TRI-STATEÉ Output® ..................................−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)..................... twice the rated IOL (mA)
ESD Last Passing Voltage (Min) .................................4000V

Temperature Min -55 deg C
Temperature Max 125 deg C
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Description

The 54F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering of 54F74 occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage of 54F74 has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

54F74 Asynchronous Inputs:

LOW input to S#D sets Q to HIGH level

LOW input to C#D sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C#D and S#D

makes both Q and Q# HIGH






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