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54F377

Features: *Ideal for addressable register applications*Clock enable for address and data synchronization applications* Eight edge-triggered D flip-flops* Buffered common clock* See 'F273 for master reset version* See 'F373 for transparent latch version* See 'F374 for TRI-STATE. version* Guaranteed...

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SeekIC No. : 004233300 Detail

54F377: Features: *Ideal for addressable register applications*Clock enable for address and data synchronization applications* Eight edge-triggered D flip-flops* Buffered common clock* See 'F273 for master ...

54F377 Data Sheet

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Part Number:
54F377
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/29

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Product Details

Description



Features:

* Ideal for addressable register applications
* Clock enable for address and data synchronization
   applications
* Eight edge-triggered D flip-flops
* Buffered common clock
* See 'F273 for master reset version
* See 'F373 for transparent latch version
* See 'F374 for TRI-STATE. version
* Guaranteed 4000V minimum ESD protection


Pinout

Connection Diagram


Specifications

Storage Temperature .........................................................................................-65 to +150
Ambient Temperature under Bias .......................................................................-55 to +125
Junction Temperature under Bias .......................................................................-55 to +175
   Plastic ..............................................................................................................-55 to +150
VCC Pin Potential to
   Ground Pin ........................................................................................................-0.5V to +7.0V
Input Voltage (Note 2) .........................................................................................-0.5V to +7.0V
Input Current (Note 2) ...................................................................................-30 mA to +5.0 mA
Voltage Applied to Output
   in HIGH State (with VCC = 0V)
   Standard Output ..................................................................................................-0.5V to VCC
   TRI-STATE® Output ...........................................................................................-0.5V to +5.5V
Current Applied to Output
   in LOW State (Max) ..............................................................................twice the rated IOL (mA)
ESD Last Passing Voltage (Min) ...........................................................................................4000V


Description

The 54F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

The register 54F377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.




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