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54F273

Features: *Ideal buffer for MOS microprocessor or memory* Eight edge-triggered D flip-flops* Buffered common clock* Buffered, asynchronous Master Reset* See 'F377 for clock enable version* See 'F373 for transparent latch version* See 'F374 for TRI-STATE. version* Guaranteed 4000V minimum ESD prote...

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SeekIC No. : 004233291 Detail

54F273: Features: *Ideal buffer for MOS microprocessor or memory* Eight edge-triggered D flip-flops* Buffered common clock* Buffered, asynchronous Master Reset* See 'F377 for clock enable version* See 'F373...

54F273 Data Sheet

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Part Number:
54F273
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

* Ideal buffer for MOS microprocessor or memory
* Eight edge-triggered D flip-flops
* Buffered common clock
* Buffered, asynchronous Master Reset
* See 'F377 for clock enable version
* See 'F373 for transparent latch version
* See 'F374 for TRI-STATE. version
* Guaranteed 4000V minimum ESD protection


Pinout

Connection Diagram


Specifications

Storage Temperature .........................................................................................-65 to +150
Ambient Temperature under Bias .......................................................................-55 to +125
Junction Temperature under Bias .......................................................................-55 to +175
   Plastic ..............................................................................................................-55 to +150
VCC Pin Potential to
   Ground Pin ........................................................................................................-0.5V to +7.0V
Input Voltage (Note 2) .........................................................................................-0.5V to +7.0V
Input Current (Note 2) ...................................................................................-30 mA to +5.0 mA
Voltage Applied to Output
   in HIGH State (with VCC = 0V)
   Standard Output ..................................................................................................-0.5V to VCC
   TRI-STATE® Output ..........................................................................................-0.5V to +5.5V
Current Applied to Output
   in LOW State (Max) .............................................................................twice the rated IOL (mA)
ESD Last Passing Voltage (Min) ..........................................................................................4000V


Description

The 54F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register 54F273 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs of 54F273 will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The 54F273 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.




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