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54ACT11109

Features: • Inputs Are TTL-Voltage Compatible• Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise• EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process• 500-mA Typical Latch-Up Immunity at 125°...

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SeekIC No. : 004233139 Detail

54ACT11109: Features: • Inputs Are TTL-Voltage Compatible• Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise• EPIC...

54ACT11109 Data Sheet

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Part Number:
54ACT11109
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . .  .0.5 V to 6 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . ±50 mA
Continuous output current, IO (VO = 0 to VCC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . . . . . .±100 mA
Storage temperature range  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .65°C to 150°C


Description

These 54ACT11109 contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (1PRE or 2PRE) or clear (1CLR or 2CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering of 54ACT11109 occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. 54ACT11109 also can perform as D-type flip-flops if J and K are tied together.

The 54ACT11109 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT11109 is characterized for operation from 40°C to 85°C.




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